Surface Microstrip
Trace on an outer layer over one reference plane. Fastest propagation (part of the field is in air), easiest to probe and rework — but exposed to soldermask variation and EMI.
Z₀ ≈ 40 – 120 Ω
PCBSync Engineering Tools · Field Guide
Impedance
Impedance
Control PCB
The working engineer's reference for controlled impedance design — transmission-line types, a free IPC-2141 trace impedance calculator, layout rules, TDR testing and fab-ready documentation. Everything needed to take a high-speed board from stackup to verified 50 Ω / 100 Ω copper.
±10% standard tolerance
50 / 90 / 100 Ω common targets
IPC-2141 formulas
TDR coupon verified
FIG.1 · U41
REF · IC-01 / OVERVIEW
What Is an Impedance Control PCB?
An impedance controlled PCB is a board on which selected traces are engineered as transmission lines with a defined characteristic impedance — typically 50 Ω single-ended or 85–120 Ω differential — held within a specified tolerance (±10% standard). When a signal's edge rate is fast relative to the length of the copper it travels on, the trace stops behaving like a simple wire: any mismatch between driver, trace and receiver impedance causes reflections, ringing, overshoot and eye-diagram closure that corrupt data.
Impedance is set by geometry and materials: trace width and thickness, dielectric height to the reference plane, dielectric constant (εr/Dk) and, for coupled pairs, the gap between traces. The designer picks the topology and target; the fabricator fine-tunes line widths to the measured properties of their laminate and verifies the result by TDR on test coupons built into the production panel.
This page is a practical, single-page reference. For deeper manufacturing-side documentation — stackup construction, material Dk tables and fab capability — see PCBSync's complete Impedance Control PCB guide.
REF · IC-02 / STRUCTURES
Impedance Control Types
Six controlled-impedance transmission line structures cover nearly every PCB. The choice is set by which layer the signal routes on and whether the net is single-ended or a differential pair.
Embedded Microstrip
Outer-layer trace buried under resin or soldermask. More stable and predictable than surface microstrip — the covering dielectric lowers impedance 2–5 Ω, so it must be modeled.
Z₀ ≈ 35 – 110 ΩSymmetric Stripline
Inner-layer trace centered between two planes. Best EMI shielding and the most consistent impedance — homogeneous dielectric, no soldermask effects. Slower propagation than microstrip.
Z₀ ≈ 30 – 100 ΩAsymmetric Stripline
Inner trace offset between unequally spaced planes — the reality of most dense stackups. Couples mainly to the nearer plane; both dielectric heights matter for the impedance model.
Z₀ ≈ 30 – 100 ΩDifferential Microstrip
Edge-coupled pair on an outer layer. Zdiff is set by width and gap — tighten S to lower impedance and improve common-mode noise rejection. Used for USB, HDMI, Ethernet at the connector.
Zdiff ≈ 80 – 120 ΩDifferential Stripline
Coupled pair on an inner layer between planes. The premium choice for long PCIe / SerDes runs: shielded, low skew, tightest tolerance. Broadside-coupled variants stack the pair vertically.
Zdiff ≈ 80 – 120 ΩAlso common: coplanar waveguide with ground (CPWG) — a surface trace flanked by via-stitched copper pours, the standard structure for RF feeds and antenna lines at 50 Ω.
REF · IC-03 / TOOL
Impedance Control Calculator
Live IPC-2141 closed-form solver for the four workhorse structures. Enter your stackup geometry — or enter a target impedance and let it solve the trace width for you.
UNITS
⌖ Reverse solve — target impedance → trace width
Z₀ · CHARACTERISTIC IMPEDANCE
—Ω
±10% window: —
εeff
—
Delay ps/in
—
Delay ps/mm
—
Common interface targets
| 50 Ω SE | RF / clocks / general single-ended |
| 75 Ω SE | Video, coax interfaces |
| 85 Ω diff | PCI Express |
| 90 Ω diff | USB 2.0 / 3.x |
| 100 Ω diff | Ethernet · LVDS · HDMI · SerDes |
| 120 Ω diff | CAN bus |
MODEL: IPC-2141 closed-form approximations · microstrip valid for 0.1 < W/H < 2.0 and εr < 15 · differential coupling terms per IPC-2141/National AN-905. Accuracy is typically within a few percent in the valid range — for sign-off, confirm with a 2D field solver and your fabricator's measured stackup. Geometry assumes the εr of the laminate at your operating frequency.
REF · IC-04 / LAYOUT
Impedance Control PCB Design Tips
Ten field-proven rules. Most controlled-impedance failures are not calculation errors — they are reference-plane and documentation errors.
TP01
Design the stackup first
Impedance lives in the stackup, not the schematic. Lock layer count, dielectric heights and copper weights with your fabricator before routing — then derive widths from their measured Dk.
TP02
Never cross plane splits
A controlled trace needs a solid, unbroken reference plane for its entire run. Crossing a split or void detours the return current, spiking impedance and radiating EMI.
TP03
Keep differential pairs symmetric
Match length with serpentine tuning near the mismatch source, keep both legs on the same layer, give each leg identical via counts, and maintain constant gap end-to-end.
TP04
Respect the 3W rule
Keep controlled traces at least 3× their width from other signals (center-to-center), and ≥2× the dielectric height away from copper pours that would load the line.
TP05
Manage via stubs
Every layer change is a discontinuity. Minimize vias on impedance nets, place ground return vias adjacent, and back-drill stubs on links above ~5 GHz.
TP06
Account for soldermask
Soldermask over a surface microstrip drops impedance 2–5 Ω. Either model it, route critical lines as stripline, or specify mask-defined impedance to the fab.
TP07
Don't trust default εr
"FR-4" spans Dk 3.8–4.8 depending on resin content, glass weave and frequency. Use the laminate datasheet value at your operating frequency — or the fab's measured number.
TP08
Spec tolerance only where needed
±10% is standard; ±7–8% costs more; ±5% constrains material choice. Call out controlled nets explicitly in a fab-note table — don't blanket the whole board.
TP09
Mind copper roughness & weave
Above ~10 GHz, copper foil roughness adds loss and effective Dk; glass-weave skew can break pairs. Use smooth foils, spread-glass laminates, and rotate routing ~10° off the weave axis.
TP10
Demand coupons + TDR report
Require impedance coupons on the panel and a TDR measurement report with your boards. If it wasn't measured, it isn't controlled — it's hoped.
REF · IC-05 / VERIFICATION
Impedance Control Testing
Controlled impedance is verified with a Time Domain Reflectometer (TDR). The instrument launches a fast voltage step (~35 ps edge) into a trace and watches the reflections: any change in impedance along the line bounces part of the edge back, and the timing of each reflection maps directly to a physical location on the board.
Because production boards rarely have probe-friendly controlled traces, fabricators build test coupons — short representative line structures — into the waste area of every panel. The coupon shares the exact stackup, copper and etch process of your board, so its measured impedance certifies the whole panel.
- Coupon designOne coupon structure per controlled layer/topology, with probe-able launches.
- TDR launchA calibrated step is injected; the reflected waveform is captured against time.
- Measurement windowImpedance is read in the settled region of the trace, excluding launch artifacts.
- Report & acceptanceEach coupon is logged against target ±tolerance; panels outside the window are rejected. RF builds may add VNA S-parameter data.
REF · IC-06 / FABRICATION
Impedance Control PCB Manufacturing
The fabricator owns the final few percent: they re-model your targets against measured laminate Dk and etch compensation, tune widths, and prove the result on coupons. Your job is to hand over unambiguous requirements.
| Class | Window | Notes |
|---|---|---|
| Standard | ±10% | Default for most digital interfaces; routine on FR-4. |
| Tight | ±7–8% | Small premium; needs well-characterized laminates. |
| Premium | ±5% | Selected stackups/materials only; discuss feasibility early. |
| Material | Dk @1GHz | Df | Use |
|---|---|---|---|
| Standard FR-4 | 4.2–4.6 | ~0.020 | General digital to ~5 GHz |
| Low-Dk FR-4 / High-Tg | 3.8–4.2 | ~0.012 | Faster digital, better stability |
| Megtron 6 | 3.6 | 0.004 | High-speed SerDes, backplanes |
| Rogers RO4350B | 3.48 | 0.0037 | RF / microwave hybrids |
| PTFE-based | 2.1–2.5 | ~0.001 | mmWave, antennas |
REF · IC-07 / INTERFACES
Where Impedance Control PCBs Are Required
90 Ω DIFF
USB 2.0 / 3.x
480 Mbps – 20 Gbps · connector-to-PHY pairs
85 Ω DIFF
PCI Express
Gen3–Gen6 · 8–64 GT/s SerDes lanes
100 Ω DIFF
Ethernet
100BASE-T → 10GBASE-T · MDI pairs to magnetics
100 Ω DIFF
HDMI / DisplayPort
TMDS & main-link lanes · up to 80 Gbps aggregate
40–60 Ω SE
DDR3/4/5 Memory
Data/address SE + 80–100 Ω strobe & clock pairs
50 Ω SE
RF & Antenna
WiFi, BT, GNSS, cellular, radar · CPWG feeds
100 Ω DIFF
LVDS / SerDes / Optics
Displays, FPGA links, SFP/QSFP modules
100–120 Ω
Automotive Networks
CAN-FD 120 Ω · 100BASE-T1 / FlexRay 100 Ω
REF · IC-08 / Q&A
Impedance Control PCB FAQ
What is an impedance control PCB?
A board on which specific traces are designed and fabricated as transmission lines with a defined characteristic impedance — e.g. 50 Ω single-ended or 100 Ω differential — held within a stated tolerance such as ±10%. The fabricator tunes trace width, dielectric height and material to hit the target and proves it by TDR measurement on test coupons.
When do I need controlled impedance?
When the signal's rise time is fast relative to the trace's propagation delay — roughly, when the trace's electrical length exceeds 1/6 of the rise time. On FR-4 that's about 1 inch (25 mm) per nanosecond of edge. In practice: USB, PCIe, Ethernet, HDMI, DDR, SerDes, RF, and anything above ~50 MHz with fast edges.
What tolerance is standard?
±10% is the industry default and is routinely achievable on FR-4. ±7–8% is available at quality fabs for a small premium; ±5% is possible on selected stackups and well-characterized laminates. Specify the tight window only on the nets that need it.
Single-ended vs differential impedance — what's the difference?
Z₀ (single-ended) is one trace referenced to a plane, typically 40–75 Ω. Zdiff is the impedance between the two legs of a coupled pair driven differentially, typically 85–120 Ω — slightly less than 2×Z₀ because coupling between the traces lowers the odd-mode impedance.
How is impedance tested on a finished PCB?
With a Time Domain Reflectometer on coupons fabricated in the panel waste area alongside your boards. The TDR launches a ~35 ps edge and reads impedance versus distance; each coupon is reported against target ± tolerance. RF designs may add VNA S-parameter characterization.
Does soldermask or copper weight change impedance?
Yes. Soldermask over surface microstrip lowers Z by 2–5 Ω; heavier copper (greater T) also lowers Z and changes the etched trapezoid shape. Both are why the fab's final modeled widths can differ slightly from your CAD values — and why you should let them adjust.